Computers

Delivers 64 GT/s Performance For Next-Gen Data Centers With PAM4 Signaling

Rambus has just announced its brand new PCIe 6.0 controller which will utilize PAM4 signaling and offer up to 64 GT/s transfer speeds on next-gen data centers. The new controller is fully compliant with PCI-SIG’s PCIe 6.0 specifications which were released earlier this month.

Rambus PCIe 6.0 Controller Announced: PAM4 Signaling & 64 GT/s Transfer Speeds For Next-Gen Data Centers

Press Release: Rambus Inc, a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express (PCIe) 6.0 Controller. The PCIe specification is the interconnect of choice across a broad landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace.

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Optimized for power, area, and latency, the Rambus PCIe 6.0 controller delivers data rates up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links against physical attacks.

“The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area”

“The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power, and area,” said Sean Fan, chief operating officer at Rambus. “As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs.”

Key features of the Rambus PCIe 6.0 Controller include:

  • Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
  • Supports fixed-sized FLITs that enable high-bandwidth efficiency
  • Implements low-latency Forward Error Correction (FEC) for link robustness
  • Internal data path size automatically scales up or down (256, 512, 1024 bits) based on max. link speed and width for reduced gate count and optimal throughput
  • Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
  • Supports Endpoint, Root-Port, Dual-Mode, and Switch port configurations
  • Integrated IDE optimized for performance

PCIe 6.0 delivers 64 GT/s transfer speeds, offers two times data rates compared to PCIe 5.0

How the PCIe 6.0 Controller Works

The PCIe 6.0 controller is backward compatible with the PCIe 5.0, 4.0, and 3.1/3.0 specifications. It supports version 6.x of the PHY Interface for PCI Express (PIPE) specification. The controller exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.

PCI Express layer

  • Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
  • Supports SerDes Architecture PIPE 10b/20b/40b/80b width
  • Supports original PIPE 8b/16b/32b/64b/128b width
  • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
  • Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
  • Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
  • Supports PCIe 6.0 to PCIe 1.0 speeds
  • Supports Forward Error Correction (FEC) – Lightweight algorithm for low latency
  • Supports L0p Low Power mode
  • Up to 4-bit parity protection for data path
  • Supports Clock Gating and Power Gating
  • RAS features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status, and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs




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