Intel and the U.S. Defense Advanced Research Projects Agency (DARPA) this week announced a three-year partnership to develop custom chips for defense systems. Under the terms of the deal, Intel will help DARPA convert currently used field-programmable gate arrays (FPGAs) into so-called structured ASICs (or eASICs), build new structured ASICs for DARPA’s needs, develop custom multi-chiplet platforms for DARPA and manufacture those new custom chips at its Fab 42 using its 10nm technology.
“We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end,” José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group, said in a statement.
“This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process.”
Structured ASICs (application-specific integrated circuits) sit between traditional ASICs and FPGAs. They rely on eCells that are pre-constructed and pre-characterized and can be configured using only a single custom layer (just like FPGAs) by means of a simple FPGA-like design flow. Just like ‘true’ ASICs, structured ASICs can support capabilities like clock balancing, power droop, signal integrity analysis, memory built-in self-test (BIST) and built-in self-repair (BISR). In short, structured ASICs can be developed in a relatively short time, yet are faster and consume less power than FPGAs.
Nowadays, DARPA uses loads of FPGAs for its applications, as building ASICs takes a lot of time and money and can compromise security. There are benefits to converting FPGAs into structured ASICs, but it does not introduce any new capabilities. So, the most interesting part of the announcement is that Intel will offer DARPA specially designed platforms for its future needs. These platforms will use chiplets featuring advanced interface bus die-to-die interconnect and embedded multi-die packaging technology to integrate heterogeneous dies into a single package.
The new chips will come from Intel’s Arizona fab with one of its 10nm fabrication technologies, which Intel does not use this process for its structured ASICs offerings.
There’s an economical advantage in using ASICs over FPGAs. Most advanced FPGAs are produced outside of the U.S., so their sales don’t directly contribute to the U.S. economy. Along with the Intel partnership, DARPA also announced its Structured Array Hardware for Automatically Realized Applications (SAHARA) program, which aims to expand usage of structured ASICs manufactured domestically in a secure environment.
The SAHARA program has two goals: switch existing applications from FPGAs to structured ASICs and then use newly designed custom structured ASICs for future military applications.
Manually converting FPGAs to structured ASICs is a complex, lengthy and costly process. To accomplish SAHARA’s goals, Intel will automate the conversion process for both currently fielded FPGAs as well as future applications.
The new chips will also feature protections to address supply chain security threats. Intel will develop the security countermeasures in collaboration with the University of Florida, Texas A&M and University of Maryland.
“SAHARA aims to enable a 60% reduction in design time, a 10X reduction in engineering costs, and a 50 percent reduction in power consumption by automating the FPGA-to-Structured ASICs conversion,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office. “The partnership with Intel will ultimately afford the DoD with significant cost and resource savings while enabling the use of leading-edge microelectronics across a host of applications.”