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Synopsys Plans To Launch The First Complete PCI Express 6.0 IP Solution In Q3 2021, Doubles The Performance Of The PCIe 5.0 Specification

Synopsys Plans To Launch The First Complete PCI Express 6.0 IP Solution In Q3 2021, Doubles The Performance Of The PCIe 5.0 Specification

The implementation of PCIe Gen 4 on mainstream consumer motherboards is quite recent, but Synopsys isn’t waiting around to upgrade. Synopsys is looking to launch a complete PCI Express 6.0 solution including the controller, PHY, and verification IP. It may not be coming into consumers’ hands in the near future, but it does allow for the early development and implementation of PCIe 6.0 system-on-chip (SoC) designs.

Synopsis’ PCI Express 6.0 Specification Doubles The Performance Of The Largely Unreleased PCIe 5.0 Specification

The foundation of PCIe Gen 6 is their very own DesignWare IP that has the best features including 64 GT/s PAM-4 signaling, FLIT mode, and L0p power state. The DesignWare Controller for PCIe 6.0 utilizes a MultiStream architecture. The performance of the MultiStream architecture doubles that of the single-stream architecture. The 1024-bit architecture on the controller allows 64 GT/s x16 bandwidth while closing timing at 1GHz. The VC Verification IP for PCIe uses native SystemVerilog/UVM architecture which is easily configurable.

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The DesignWare PHY IP takes advantage of unique adaptive DSP algorithms. These algorithms optimize analog and digital equalization to maximize power efficiency regardless of the channel. On top of that, it minimizes package crosstalk and allows dense SoC integration for x16 links. The PHP also enables near-zero link downtime using diagnostic features. The ADC-based architecture in combination with the optimized datapath allows for ultra-low latency. John Koeter, senior vice president of marketing and strategy for IP at Synopsys, described the use and strengths of the PCIe Gen 6 specifications below:

“Advanced cloud computing, storage and machine learning applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems. With Synopsys’ complete DesignWare IP solution for PCI Express 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys’ proven expertise and established leadership in PCI Express to accelerate their path to silicon success.”

The complete IP solution from Synopsys addresses evolving latency, bandwidth, and power-efficiency requirements of high-performance computing, AI, and storage SoCs. Although these advancements are great, it will be quite some time before consumers have PCIe 6.0 support as we have just scratched the surface of PCIe 4.0 and 5.0 hasn’t made its way onto consumer motherboards. PCIe 5.0 will be making its way onto the server platforms in 2022 with the Eagle Stream platform of Xeon processors from Intel and the Genoa platform of Epyc processors from AMD.

The DesignWare Controller and PHY IP for PCIe 6.0 will be available in Q3 of 2021 whilst the verification IP is currently available. It will take some time for PCIe 6.0 to be implemented in servers let alone consumer motherboards.




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